1. Field of the Invention
The present invention relates to a drive circuit of the power device, which prevents faulty operations by dv/dt transient signals.
2. Description of the Background Art
FIG. 7 shows a circuit of a semiconductor device 100, having a conventional drive circuit of the power device. In FIG. 7, the circuit has the power source 20 to supply the power source electric potential Vdd against the ground electric potential COM and the half-bridge type power device 19 which includes totem pole-connected power device 17, 18, e.g.IGBT (insulating gate bipolar transistor) installed between the power source electric potential Vdd and the ground electric potential COM. Power devices 17, 18 are reverse and parallel connected to the free-wheel-diode D1 and D2. Moreover, the load (the inductive load, e.g. motors) is connected between a connecting node N1 of power devices 17 and 18, and the ground electric potential COM.
The power device 17 is a device switching between the potential at the connecting node N1 as a standard electric potential and the power source electric potential Vdd supplied by the power source20. The power device 17 is called high electric potential side power device. Contrary, the power device 18 is called low electric potential side power device.
Also, the semiconductor device 100 shown in FIG. 7, comprises a drive circuit HD of high electric potential side power device and a drive circuit LD of low electric potential side power device, but an explanation about the drive circuit LD of low electric potential side power device is omitted, because the drive circuit LD relates less to the present invention.
Following description explains about a structure of the high electric potential side power device. Two outputs of a pulse generation circuit 1 generating pulsed on-signals and off-signals corresponding to input signals given from a microcomputer provided outside, are connected to gate electrodes of high-voltage N-channel MOS (HNMOS) transistors 2 and 3 which functions as a level shift transistor. Each of drain electrodes of HNMOS transistors 2 and 3, is connected to one ends of resistances 4 and 5, moreover these electrodes are connected to inputs of inverter circuits 6 and 7, too. Also, the ground electric potential COM is given to both of source electrodes of HNMOS transistors 2 and 3.
Moreover, outputs of inverter circuits 6 and 7, are connected to set input and reset input of not-inversed-input-typed set-reset-flip-flop circuit 10. The output Q of said set-reset-flip-flop circuit 10 is connected to a gate electrode of NMOS transistor 12, and the output Q is connected to an input of the inverter circuit 11, too. Also, the output of the inverter circuit 11 is connected to the gate electrode of NMOS transistor 13. The source electrode of NMOS transistor 12 is connected to the drain electrode of NMOS transistor 13, and that source electrode is connected to the gate electrode of power device 17, too. High electric potential side power source 16 is provided between the drain electrode of NMOS transistor 12 and the connecting node N1.
Other ends of resistances 4 and 5 are connected to the drain electrode of NMOS transister12, or, positive potential output of high electric potential side power source 16. Also, the source electrode of NMOS transistor 13, or, negative potential output of high electric potential side power source 16, is connected to anode of diode 8 and that source electrode is connected to anode of diode of a diode 9, too. The cathode of diode 8, 9 are connected to the drain electrodes of HNMOS transistor 2 and 3, respectively.
In said drive circuit HD of high electric potential side power device, dv/dt transient signal which is spread signal of quick transition of voltage, occurs in the line (the line is called line L1 hereinafter) between the connecting node N1 and anodes of diode 8, 9 depending on the switching condition of the half-bridge type power device 19. Then electric current (the electric current is called dv/dt electric current hereinafter) which is given by the product of the parasitic capacity C and dv/dt transient signal, flows to HNMOS transistors 2 and 3 simultaneously.
Moreover, dv/dt electric current flowing to HNMOS transistors 2 and 3, has same level of the electric current flowing in ordinary switching, so voltage drops occur at resistance 4 and 5 at the same time. As a result, xe2x80x9cHxe2x80x9d (positive value in active high) as set input and reset input of set-reset-flip-flop circuit 10, is simultaneously given to the set-reset-flip-flop circuit 10. In general, it is impermissible that xe2x80x9cHxe2x80x9d is simultaneously given to the set input and the reset input of non-inversed-input-type set-reset-flip-flop circuit, and the operation which can""t be forecasted, in short, mis-operation is caused.
A protection circuit 26b using the logic circuit showing in FIG. 8 is provided between a level-shift circuit 25 level-shifting on-signals and off-signals of the pulse generation circuit1 and the set-reset-flip-flop circuit 10 to prevent such mis-operations. A following description explains about the structure of the protection circuit 26b. The protection circuit 26b has the NAND circuit G101 which is inputted level-shifted on-signals namely output of the inverter circuit 7 as the first level-shifted signal, and the NAND circuit G121 which is inputted level-shifted off-signals namely output of the inverter circuit 6 as the second level-shifted signal, and the NAND circuit G111 which is inputted the first and second level-shifted signals, in the first stage. Series connected inverter circuits G102, G104 are connected to the NAND circuit G101, and series connected inverter circuits G122, G124 are connected to the NAND circuit G121, and the inverter circuit G112 is connected to the NAND circuit G111. Moreover, outputs of the inverter circuits G104, G112 are inputted to the NOR circuit G13, and outputs of the inverter circuits G124, G112 are inputted to the NOR circuit G14. These outputs of NOR circuit G13, G14 are set-signals and reset-signals to the set-reset flip-flop circuit 10.
When dv/dt transient signal flows to the line L1, the first and second level-shifted signals are simultaneously inputted to the protection circuit 26b. At the time, logic value of signal passing through the NAND circuit G101, the inverter circuits G102, G104 and signal passing through the NAND circuit G121, the inverter circuits G122, G124 are opposite to the logic value of signal passing through the NAND circuit G111 and the inverter circuit G112, so the NOR circuit G13 prevents outputting the set signal to the set-reset-flip-flop circuit 10. The NOR circuit G14 prevents outputting the reset signal to the set-reset-flip-flop circuit 10 as well as the NOR circuit G13. As the result, the structure according to above prevents mis-operations of set-reset-flip-flop circuit 10.
However there is a gate delay at each logic circuits composing the protection circuit 26b. In the case of thinking strictly about the gate delay, the protection circuit 26b can not prevent always mis-operations of the set-reset-flip-flop circuit 10. In other words, the number of logic circuits which signal passing through the NAND circuit G101, the inverter circuits G102, G104 and signal passing through the NAND circuit G121, the inverter circuits G122, G124 go through, is different from the number of logic circuits which signal passing through the NAND circuit G111 and the inverter circuit G112 goes through, so the transient hazard happened.
Following description explains about said phenomenon using the timing chart showing in FIG. 9. When the transient dv/dt signal flows to the line L1, at first the displacement currents flow through the parasitic capacity of the HNMOS transistor 2, 3 and electric potentials at VR1, VR2 which are input terminals of the inverter circuits 6, 7, fall down by voltage drop by the displacement currents and resistances 4, 5. When electric potentials at VR1, VR2 are lower than logic threshold of xe2x80x9cLxe2x80x9d (negative value in active High) of the inverter circuits 6, 7, the logic values at B,C which are output terminals of the inverter circuits 6, 7 turn over. In FIG. 9, the period is indicated by Tv.
If the logic values at B and C change xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d, the logic values at D, E which are output terminals of the inverter circuits G104, G124, and at F which is output terminal of the inverter circuit G112, and at G, H which are output terminals of the NOR circuits G13, G14, are changed respectively. Hereinbelow, there are 3 gates between B and D, C and E, and there are 2 gates between B, C and F. Therefore, logic value at F changes xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d at first, then logics value at D, E is delayed for one gate, and changes xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d. There is no problem in this case, because inputs to the NOR circuit G13, G14 do not become xe2x80x9cLxe2x80x9d simultaneously.
On the other hand, logic values at B, C change xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, logic value at F changes xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d at first, logic values at D,E are delayed for one gate, and change xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d. In this case, the period Td that xe2x80x9cLxe2x80x9d is inputted simultaneously to the NOR circuit G13, G14, happens. xe2x80x9cLxe2x80x9d at D, E, F in the period Td is sent to G and H through the NOR circuits G13, G14 (for one gate), so the set signal and the reset signal are simultaneously inputted to the set-reset-flip-flop circuit 10.
These transient hazard may be dissolved along with the improvement of devices comprising logic circuits, e.g. transistors, by decreasing delay of gate, however this problem can not be solved fundamentally by only the improvement of devices, because the change speed of set signals and reset signals of the set-reset-flip-flop circuit 10 becomes simultaneously fast. Therefore, conventional protection circuits can not prevent perfectly mis-operations of the set-reset-flip-flop circuit 10.
Apart from the protection circuit 26b, there is a problem in the pulse generation circuit 1, too. FIG. 10 shows the structure of conventional pulse generation circuit 1d. In other words, input-signal is inputted to the inverter circuits G200, G201, and the inverter circuit G202 is series-connected to the inverter circuit G201. Moreover, output signals of the inverter circuits G200, G202 are inputted to the NAND circuit G203, and the output signal of the NAND circuit G203 is outputted as off-signal through the inverter circuit G204. Also, the output signal of the inverter circuit G200 is inputted to the inverter circuits G210, G211, and the inverter circuit G212 is series-connected to the inverter circuit G212. Output signals of the inverter circuits G210, G212 are inputted to the NAND circuit G213, the output signal of the NAND circuit G213 is outputted as on-signal through the inverter circuit G214.
In the pulse generation circuit 1d, the difference of delay time of inverter and the number of inverters which signals pass through is used. In other words, the NAND circuit G203 generates the pulsed xe2x80x9cLxe2x80x9d corresponding to the difference of the spread time of change of input signal xe2x80x9cHxe2x80x9d to xe2x80x9cLxe2x80x9d, passing through the inverter circuit G200, the inverter circuits G201 and G202, and after that, the pulsed xe2x80x9cLxe2x80x9d is reversed to the pulsed xe2x80x9cHxe2x80x9d by the inverter circuit G204, so the off-signal generates. Also, the NAND circuit G213 generates the pulsed xe2x80x9cLxe2x80x9d corresponding to the difference of the spread time of change of input signal xe2x80x9cLxe2x80x9d to xe2x80x9cHxe2x80x9d, passing through the inverter circuit G210, the inverter circuits G211 and G212, and after that the pulsed xe2x80x9cLxe2x80x9d is reversed to the pulsed xe2x80x9cHxe2x80x9d by the inverter circuit G214, so the on-signal generates. FIG. 11 shows the timing chart showing said condition. The power device 17 is operated by edge-trigger of the pulsed on-signal and off-signal to restrain the consumption of the power to a minimum.
The pulse generation circuit 1d can not simultaneously generate on-signal and off-signal because this circuit has said structure. Therefore, it takes time to test the protection circuit 26b, because it must apply dv/dt transient signal from outside to check the operation of the protection circuit 26b. 
The object of the present invention is providing the protection circuit, which never inputs simultaneously set-signal and reset-signal to the set-reset-flip-flop circuit, and the pulse generation circuit, which can generate on-signal and off-signal simultaneously for the test.
According to a first aspect of the present invention, a protection circuit comprises a plurality of logic elements and delay elements, each having a predetermined amount of delay respectively, first and second input signal signals as pulse signals are inputted to the protection circuit and the protection circuit generates a plurality of inside signals by the first and second input signals passing respectively through a part of the plurality of logic elements and delay elements, the plurality of inside signals pass through a part of the plurality of logic elements and delay elements, and each of the plurality of inside signals receives different amount of delay depending on the number and/or sorts of logic elements and delay elements passed through, the protection circuit outputs first and/or second output signals transiting corresponding to the first and/or second signals respectively by logic-operating the each of the plurality of inside signals in a part of the plurality of the logic elements, when the first and second input signals transit at different time, and the protection circuit prevents transition of the first and second output signals by negating each of the plurality of the inside signals in a part of the plurality of logic elements by difference of the amount of delay received by each of the plurality of inside signals, when the first and second input signals transit simultaneously.
According to a second aspect of the present invention, a protection circuit according to claim 1, comprises a first delay element which the first input signal is inputted to, and outputs the first input signal with delaying for the amount of first delay, a second delay elements which said second input signal is inputted to, and outputs said second input signal with delaying for the amount of said first delay, a logical AND element which the first and second input signals are inputted to, and outputs an AND of the first and second input signals with delaying for the amount of the first delay, a third delay element which the output of said first delay element is inputted to, and outputs the output of the first delay element with delaying for the amount of second delay, a fourth delay element which the output of the logical AND element is inputted to, and outputs the output of the logical AND element with delaying for the amount of the second delay, a fifth delay element which the output of said second delay element is inputted to, and outputs the output of said second delay element with delaying for the amount of said second delay, a logical OR element which outputs of the logical AND element and the fourth delay element are inputted to, and outputs an OR of outputs of the logical AND element and the fourth delay element with delaying for the amount of the second delay, a first inverter element which the output of the third delay element is inputted to, and logic-reverses the output of the third delay element and outputs the output of the third delay element with delaying for the amount of third delay, a second inverter element which the output of fifth delay element is inputted to, and logic-reverses the output of the fifth delay element and outputs the output of the fifth delay element with delaying for the amount of the third delay, a first logical NOR element which outputs of the logical OR element and the first inverter element are inputted to, and logic-reverses an OR of outputs of the OR element and the first inverter element and outputs the OR as the first output signal, and a second logical NOR element which outputs of the logical OR element and the second inverter element are inputted to, and logic-reverses an OR of outputs of the logical OR element and the second inverter element and outputs the OR as the second output signal, and wherein the amount of said second delay being greater than the amount of said third delay.
According to a third aspect of the present invention, a protection circuit according to claim 2, wherein the first delay element comprises a first NAND circuit having input terminals both of which the first input signal is inputted to, and a first inverter circuit which the output of the first NAND circuit is inputted to, the second delay element comprising a second NAND circuit having input terminals both of which the second input signal is inputted to, and a second inverter circuit which the output of said second NAND circuit is inputted to, the logical AND element comprising a third NAND circuit which the first and second input signals are inputted to, and a third inverter circuit which the output signal of the third NAND circuit is inputted to, the third delay element comprising a first NOR circuit which the output of the first delay element is inputted to both of input terminals, and a fourth inverter circuit which the output of the first NOR circuit is inputted to, the fourth delay element comprising a second NOR circuit which the output of the logical AND element is inputted to both of input terminals, and a fifth inverter circuit which the output of the second NOR circuit is inputted to, the fifth delay element comprising a third NOR circuit which the output of the second delay element is inputted to both of input terminals, and a sixth inverter circuit which the output of the third NOR circuit is inputted to, the logical OR element comprising a fourth NOR circuit which the outputs of the logical AND element and the fourth delay element are inputted to, and a seventh inverter circuit which the output of the fourth NOR circuit is inputted to, the first inverter element comprising an eighth inverter circuit which the output of the third delay element is inputted to, the second inverter element comprising a ninth inverter circuit which the output of the fifth delay element is inputted to, the first logical NOR element comprising a fifth NOR circuit which the outputs of the first inverter element and the OR element are inputted to, and the second logical NOR element comprising a sixth NOR circuit which outputs of the second inverter element and the OR element are inputted to.
According to a fourth aspect of the present invention, a pulse generation circuit, wherein first input signal which level-shifts between first logic value and second logic value having the exclusive relations with the first logic value, is inputted to the pulse generation circuit, and second input signal, or, in addition to the second input signal, third input signal are inputted to the pulse generation circuit, and the pulse generation circuit outputs first pulse on level-transiting of the first input signal from the first logic value to the second logic value, and the pulse generating circuit outputs second pulse on level-transiting of the first input signal from the second logic value to said first logic value, and the pulse generating circuit outputs the first and second pulse when the second or third input signal is inputted.
According to a fifth aspect of the present invention, a pulse generation circuit according to claim 4 comprises a first inverter element which the first input signal is inputted to, and logic-reverses the first input signal and outputs the first input signal, a first delay element which the first input signal is inputted to, and outputs the first input signal with delaying from the output of the first inverter element, a first logical AND element which the outputs of the first inverter element and the first delay element are inputted to, and outputs an AND of the outputs of the first inverter element and the first delay element, a first logical OR element which the output of the first logical AND element and the first logic value are inputted to, and when the second input signal is given instead of the first logic value, the second logic value is inputted to, and outputs an OR of the output of the first logical AND element and the first logic value or the second logic value, as the second pulse, a second inverter element which the output of the first inverter element is inputted to, and logic-reverses the output of the first inverter element and outputs the output of the first inverter element, a second delay element which the output of the first inverter element is inputted to, and outputs the output of the first inverter element with delaying from the output of the second inverter element, a second logical AND element which the outputs of the second inverter element and the second delay element are inputted to, and outputs an AND of outputs of the second inverter element and the second delay element, a second logical OR element which the output of the second logical AND element and the first logic value are inputted to, and when the third input signal is given instead of the first logic value, the second logic value is inputted to, and outputs an OR of the output of the second logical AND element and the first logic value or the second logic value as the first pulse.
According to a sixth aspect of the present invention, a pulse generation circuit according to claim 5, wherein the first inverter element comprises a first inverter circuit which logic-reverses the first input signal and outputs the first input signal, the first delay element comprising a second inverter circuit which logic-reverses the first input signal and outputs the first input signal, and a third inverter circuit which logic-reverses the output of the second inverter circuit and outputs the output of the second inverter circuit, the first logical AND element comprising a first NAND circuit which the outputs of the first inverter element and the first delay element are inputted to, and a fourth inverter circuit which the output of the first NAND circuit is inputted to, the first logical OR element comprising a first NOR circuit which logic-reverses an OR of the output of the first logical AND element and the first or second logic value and outputs the OR, and a fifth inverter circuit which the output of the first NOR circuit is inputted to, the second inverter element comprising a sixth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, the second delay element comprising a seventh inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, and an eighth inverter circuit which logic-reverses the output of the seventh inverter circuit and outputs the output of the seventh inverter circuit, the second logical AND element comprising a second NAND circuit which the outputs of the second inverter element and the second delay element are inputted to, and a ninth inverter circuit which the output of the second NAND circuit is inputted to, and the second logical OR element comprising a second NOR circuit which logic-reverses an OR of the output of the second logical AND element and the first or second logic value and outputs the OR, and a tenth inverter circuit which the output of the second NOR circuit is inputted to.
According to a seventh aspect of the present invention, a pulse generation circuit according to claim 4 comprises a first inverter element which the first input signal is inputted to, and logic-reverses the first input signal and outputs the first input signal, a first delay element which the first input signal is inputted to, and outputs the first input signal with delaying from the output of the first inverter element, a first logical NAND element which the outputs of the first inverter element and the first delay element are inputted to, and logic-reverses an AND of the outputs of the first inverter element and the first delay element and outputs the AND of the outputs of the first inverter element and the first delay element, a second logical NAND element which the output of the first logical NAND element and the second logic value are inputted to, and when the second input signal is given, instead of the second logic value, the first logic value is inputted to, and logic-reverses an AND of the output of the first logical NAND element and the first or second logic value and outputs the AND as the second pulse, a second inverter element which the output of the first inverter element is inputted to, and logic-reverses the output of the first inverter element and outputs the output of the first inverter element, a second delay element which the output of the first inverter element is inputted to, and outputs the output of the first inverter element with delaying from the output of the second inverter element, a third logical NAND element which the outputs of the second inverter element and the second delay element are inputted to, and logic-reverses an AND of the outputs of the second inverter element and the second delay element and outputs the AND, a fourth logical NAND element which the outputs of the third logical NAND element and the second logic value are inputted to, when the third input signal is given, and instead of the second logic value, the first logic value is inputted to, and logic-reverses an AND of the output of the third logical NAND element and the first or second logic value and outputs the AND as the first pulse.
According to an eighth aspect of the present invention, a pulse generation circuit according to claim 7, wherein the first inverter element comprises a first inverter circuit which logic-reverses said first input signal and outputs said first input signal, the first delay element comprising a second inverter circuit which logic-reverses the first input signal and outputs the first input signal, and a third inverter circuit which logic-reverses the output of the second inverter circuit and outputs the output of the second inverter circuit, the first logical NAND element comprising a first NAND circuit which the outputs of the first inverter element and the first delay element are inputted to, the second logical NAND element comprising a second NAND circuit which the outputs of the first NAND element and the first or second logic value are inputted to, the second inverter element comprising a fourth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, the second delay element comprising a fifth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, and a sixth inverter circuit which logic-reverses the output of the fifth inverter circuit and outputs the output of the fifth inverter circuit, the third logical NAND element comprising a third NAND circuit which the outputs of the second inverter element and the second delay element are inputted to, and the fourth logical NAND element comprising a fourth NAND circuit which the outputs of the third logical NAND element and the first or second logic value are inputted to.
According to a ninth aspect of the present invention, a pulse generation circuit according to claim 4 comprises a first inverter element which the first input signal is inputted to, and logic-reverses the first input signal and outputs the first input signal, a first delay element which the first input signal is inputted to, and outputs the first input signal with delaying from the output of the first inverter element, a first logical AND element which the outputs of the first inverter element and the first delay element are inputted to, and outputs an AND of outputs of the first inverter element and the first delay element, a second inverter element which the output of the first inverter element is inputted to, and logic-reverses the output of the first inverter element and outputs the output of the first inverter element, a second delay element which the output of the first inverter element is inputted to, and outputs the output of the first inverter element with delaying from the output of the second inverter element, a second logical AND element which the outputs of the second inverter element and the second delay element are inputted to, and outputs an AND of outputs of the second inverter element and the second delay element, a third logical AND element which the outputs of the second logical AND element and the first logic value are inputted to, and when the second input signal is given, instead of the first logic value, the second logic value is inputted to, and outputs an AND of the output of the second logical AND element and the first or second logic value with delaying for the amount of first delay, a fourth logical AND element which logic-reversed the first logic value and the output of the first logical AND element are inputted to, and when the second input signal is given, instead of logic-reversed the first logic value, logic-reversed the second logic value is inputted to, and outputs an AND of the output of the first logical AND element and logic-reversed the first or second logic value with delaying for the amount of the first delay, a logical OR element which the outputs of the third and fourth logical AND elements are inputted to, and outputs an OR of the third and fourth logical AND elements with delaying for the amount of second delay, as the second pulse, and when the second input signal is given, outputs the first and the second pulses simultaneously, a third delay element which the output of the second logical AND element is inputted to, and outputs the output of the second logical AND element with delaying for the amount of the first delay, and a fourth delay element which the output of the third delay element is inputted to, and outputs the output of the third delay element with delaying for the amount of the second delay, as the first pulse.
According to a tenth aspect of the present invention, a pulse generation circuit according to claim 9, wherein the first inverter element comprises a first inverter circuit which logic-reverses the first input signal and outputs the first input signal, the first delay element comprising a second inverter circuit which logic-reverses the first input signal and outputs the first input signal, and a third inverter circuit which logic-reverses the output of the second inverter circuit and outputs the output of the second inverter circuit, the first logical AND element comprising a first NAND circuit which the outputs of the first inverter element and the first delay element are inputted to, and a fourth inverter circuit which the output of the first NAND circuit is inputted to, the second inverter element comprising a fifth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, the second delay element comprising a sixth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, and a seventh inverter circuit which logic-reverses the output of the sixth inverter circuit and outputs the output of the sixth inverter circuit, the second logical AND element comprising a second NAND circuit which the outputs of the second inverter element and the second delay element are inputted to, and an eighth inverter circuit which the output of the second NAND circuit is inputted to, the third logical AND element comprising a third NAND circuit which logic-reverses an AND of the output of the second logical AND element and the first or second logic value and outputs the AND, and a ninth inverter circuit which the output of the third NAND circuit is inputted to, the fourth logical AND element comprising a fourth NAND circuit which logic-reverses an AND of the output of the first logical AND element and logic-reversed the first or second logic value and outputs the AND, and a tenth inverter circuit which the output of the fourth NAND circuit is inputted to, the logical OR element comprising a first NOR circuit which logic-reverses an OR of the outputs of the third and fourth logical AND element and outputs the OR, and an eleventh inverter circuit which the output of the first NOR circuit is inputted to, the third delay element comprising a fifth NAND circuit which logic-reverses an AND of the output of the second logical AND element and the second logic value and outputs the AND, and a twelfth inverter circuit which the output of the fifth NAND circuit is inputted to, and the fourth delay element comprising a second NOR circuit which logic-reverses an OR of the output of the third delay element and the first logic value and outputs the OR, and a thirteenth inverter circuit which the output of the second NOR circuit is inputted to.
According to an eleventh aspect of the present invention, a drive circuit for driving a switching device comprises control means which control conductive condition of the switching device, pulse generation means which generates first and second pulse signals respectively corresponding to level transient of rising-up and falling-down of input signal, and level shifting means which level-shifts the first and second pulse signals to generate first and second level-shifted signals respectively corresponding to the first and second pulse signals, wherein the first pulse signal is on-signal which turns on the switching device, the second pulse signal is off-signal which turns off the switching device, the control means comprises control signal outputting means for outputting a control signal which keeps the switching device turning-on or turning-off depending on the first and second level-shifted signals, and protection means provided at pre-stage of the control signal outputting means for giving a predetermined signal to the control signal outputting means to keep the control signal outputting means outputting said control signal just before when the first and second level-shifted signals are given simultaneously, the control signal outputting means is a set-reset-flip-flop circuit, and the protection means is a protection circuit according to claim 1, the first and second input signals correspond to the first and second level-shifted signals respectively, the first output signal corresponds to set-signal to the set-reset-flip-flop circuit and the second output signal corresponds to reset-signal to the set-reset-flip-flop circuit.
According to a twelfth aspect of the present invention, a drive circuit according to claim 11 wherein the protection circuit comprises a first delay element which the first input signal is inputted to, and outputs the first input signal with delaying for the amount of first delay, a second delay element which the second input signal is inputted to, and outputs the second input signal with delaying for the amount of the first delay, a logical AND element which the first and second input signals are inputted to, and outputs an AND of the first and second input signals with delaying for the amount of the first delay, a third delay element which the output of the first delay element is inputted to, and outputs the output of the first delay element with delaying for the amount of second delay, a fourth delay element which the output of the logical AND element is inputted to, and outputs the output of the logical AND element with delaying for the amount of the second delay, a fifth delay element which the output of the second delay element is inputted to, and outputs the output of the second delay element with delaying for the amount of the second delay, a logical OR element which outputs of the logical AND element and the fourth delay element are inputted to, and outputs an OR of outputs of the logical AND element and the fourth delay element with delaying for the amount of the second delay, a first inverter element which the output of the third delay element is inputted to, and logic-reverses the output of the third delay element and outputs the output of the third delay element with delaying for the amount of third delay, a second inverter element which the output of the fifth delay element is inputted to, and logic-reverses the output of the fifth delay element and outputs the output of the fifth delay element with delaying for the amount of the third delay, a first logical NOR element which outputs of the logical OR element and the first inverter element are inputted to, and logic-reverses an OR of outputs of the OR element and the first inverter element and outputs the OR as the first output signal, and a second NOR element which outputs of the logical OR element and the second inverter element are inputted to, and logic-reverses an OR of outputs of the OR element and the second inverter element and outputs the OR as the second output signal, wherein the amount of the second delay is greater than the amount of the third delay.
According to a thirteenth aspect of the present invention, a drive circuit according to claim 12 wherein the first delay element comprises a first NAND circuit having input terminals both of which the first input signal is inputted to, and a first inverter circuit which the output of the first NAND circuit is inputted to, the second delay element comprising a second NAND circuit having input terminals both of which said second input signal is inputted to, and a second inverter circuit which the output of the second NAND circuit is inputted to, the logical AND element comprising a third NAND circuit which the first and the second input signals are inputted to, and a third inverter circuit which the output of the third NAND circuit is inputted to, the third delay element comprising a first NOR circuit which the output of the first delay element is inputted to both of input terminals, and a fourth inverter circuit which the output of the first NOR circuit is inputted to, the fourth delay element comprising a second NOR circuit which the output of the logical AND element is inputted to both of input terminals, and a fifth inverter circuit which the output of the second NOR circuit is inputted to, the fifth delay element comprising a third NOR circuit which the output of the second delay element is inputted to both of input terminals, and a sixth inverter circuit which the output of the third NOR circuit is inputted to, the logical OR element comprising a fourth NOR circuit which the outputs of the logical AND element and the fourth delay element are inputted to, and a seventh inverter circuit which the output of the fourth NOR circuit is inputted to, the first inverter element comprising an eighth inverter circuit which the output of the third delay element is inputted to, the second inverter element comprising a ninth inverter circuit which the output of the fifth delay element is inputted to, the first logical NOR element comprising a fifth NOR circuit which the outputs of the first inverter element and the OR element are inputted to, and the second logical NOR element comprising a sixth NOR circuit which the outputs of the second inverter element and the OR element are inputted to.
According to a fourteenth aspect of the present invention; a drive circuit for driving a switching device comprises control means which control conductive condition of the switching device, pulse generation means which generates first and second pulse signals respectively corresponding to level transient of rising-up and falling-down of input signal, level shifting means which level-shifts the first and second pulse signals to generate first and second level-shifted signals respectively corresponding to the first and second pulse signals, wherein the first pulse signal is on-signal which turns on the switching device, the second pulse signal is off-signal which turns off the switching device, the pulse generation means which is a pulse generation circuit according to claim 4, wherein the first input signal corresponds to the input signal and the first pulse corresponds to the first pulse signal, and the second pulse corresponds to the second pulse signal, the control means comprises control signal outputting means for outputting a control signal which keeps the switching device turning-on or turning-off depending on the first and second level-shifted signals, and protection means provided at pre-stage of the control signal outputting means for giving a predetermined signal to the control signal outputting means to keep the control signal outputting means outputting the control signal just before when the first and second level-shifted signals are given simultaneously.
According to a fifteenth aspect of the present invention, a drive circuit according to claim 14 wherein a pulse generation circuit comprises a first inverter element which the first input signal is inputted to, and logic-reverses the first input signal and outputs the first input signal, a first delay element which the first input signal is inputted to, and outputs the first input signal with delaying from the output of the first inverter element, a first logical AND element which the outputs of the first inverter element and the first delay element are inputted to, and outputs an AND of the outputs of the first inverter element and the first delay element, a first logical OR element which the output of the first logical AND element and the first logic value are inputted to, and when the second input signal is given, instead of the first logic value, the second logic value is inputted to, and outputs an OR of the output of the first logical AND element and the first logic value or the second logic value, as the second pulse, a second inverter element which the output of the first inverter element is inputted to, and logic-reverses the output of the first inverter element and outputs the output of the first inverter element, a second delay element which the output of the first inverter element is inputted to, and outputs the output of the first inverter element with delaying from the output of the second inverter element, a second logical AND element which the outputs of the second inverter element and the second delay element are inputted to, and outputs an AND of outputs of the second inverter element and the second delay element, a second logical OR element which the output of the second logical AND element and the first logic value are inputted to, and when the third input signal is given, instead of the first logic value, the second logic value is inputted to, and outputs an OR of the output of the second logical AND element and the first logic value or the second logic value as the first pulse.
According to a sixteenth aspect of the present invention, a drive circuit according to claim 15 wherein the first inverter element comprises a first inverter circuit which logic-reverses the first input signal and outputs the first input signal, the first delay element comprising a second inverter circuit which logic-reverses the first input signal and outputs the first input signal, and a third inverter circuit which logic-reverses the output of the second inverter circuit and outputs the output of the second inverter circuit, the first logical AND element comprising a first NAND circuit which the outputs of the first inverter element and the first delay element are inputted to, and a fourth inverter circuit which the output of the first NAND circuit is inputted to, the first logical OR element comprising a first NOR circuit which logic-reverses an OR of the output of the first logical AND element and the first or second logic value and outputs the OR, and a fifth inverter circuit which the output of the first NOR circuit is inputted to, the second inverter element comprising a sixth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, the second delay element comprising a seventh inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, and an eighth inverter circuit which logic-reverses the output of the seventh inverter circuit and outputs the output of the seventh inverter circuit, the second logical AND element comprising a second NAND circuit which the outputs of the second inverter element and the second delay element are inputted to, and a ninth inverter circuit which the output of the second NAND circuit is inputted to, the second logical OR element comprising a second NOR circuit which logic-reverses of the output of the second AND element and the first or second logic value and outputs the OR, and a tenth inverter circuit which the output of the second NOR circuit is inputted to.
According to a seventeenth aspect of the present invention, a drive circuit according to claim 14 wherein the pulse generation circuit comprises a first inverter element which the first input signal is inputted to, and logic-reverses the first input signal and outputs the first input signal, a first delay element which the first input signal is inputted to, and outputs the first input signal with delaying from the output of the first inverter element, a first logical NAND element which the outputs of the first inverter element and the first delay element are inputted to, and logic-reverses an AND of outputs of the first inverter element and the first delay element and outputs the AND of the outputs of the first inverter element and the first delay element, a second logical NAND element which the output of the first logical NAND element and the second logic value are inputted to, and when the second input signal is given, instead of said second logic value, the first logic value is inputted to, and logic-reverses an AND of the output of the first logical NAND element and of the first or second logic value and outputs the AND as the second pulse, a second inverter element which the output of the first inverter element is inputted to, and logic-reverses the output of the first inverter element and outputs the output of the first inverter element, a second delay element which the output of the first inverter element is inputted to, and outputs the output of the first inverter element with delaying from the output of the second inverter element, a third logical NAND element which the outputs of the second inverter element and the second delay element are inputted to, and logic-reverses an AND of the outputs of the second inverter element and the second delay element and outputs the AND, a fourth logical NAND element which the outputs of the third logical NAND element and the second logic value are inputted to, and when the third input signal is given, instead of the second logic value, the first logic value is inputted to, and logic-reverses an AND of the output of the third logical NAND element and the first or second logic value and outputs the AND as the first pulse.
According to an eighteenth aspect of the present invention, a drive circuit according to claim 17, wherein the first inverter element comprises a first inverter circuit which logic-reverses the first input signal and outputs the first input signal, the first delay element comprising a second inverter circuit which logic-reverses the first input signal and outputs the first input signal, and a third inverter circuit which logic-reverses the output of the second inverter circuit and outputs the output of the second inverter circuit, the first logical NAND element comprising a first NAND circuit which the outputs of the first inverter element and the first delay element are inputted to, the second logical NAND element comprising a second NAND circuit which the outputs of the first logical NAND element and the first or second logic value are inputted to, the second inverter element comprising a fourth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, the second delay element comprising a fifth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, and a sixth inverter circuit which logic-reverses the output of the fifth inverter circuit and outputs the output of the fifth inverter circuit, the third logical NAND element comprising a third NAND circuit which the outputs of the second inverter element and the second delay element are inputted to, and the fourth logical NAND element comprising a fourth NAND circuit which the outputs of the third logical NAND element and the first or second logic value are inputted to.
According to a nineteenth aspect of the present invention, a drive circuit according to claim 14, wherein the pulse generation circuit comprises a first inverter element which the first input signal is inputted to, and logic-reverses the first input signal and outputs the first input signal, a first delay element which the first input signal is inputted to, and outputs the first input signal with delaying from the output of the first inverter element, a first logical AND element which the outputs of the first inverter element and the first delay element are inputted to, and outputs an AND of outputs of the first inverter element and the first delay element, a second inverter element which the output of the first inverter element is inputted to, and logic-reverses the output of the first inverter element and outputs the output of the first inverter element, a second delay element which the output of the first inverter element is inputted to, and outputs the output of the first inverter element with delaying from the output of the second inverter element, a second logical AND element which the outputs of the second inverter element and the second delay element are inputted to, and outputs an AND of outputs of the second inverter element and the second delay element, a third logical AND element which the outputs of the second AND element and the first logic value are inputted to, and when the second input signal is given, instead of the first logic value, the second logic value is inputted to, and outputs an AND of the output of the second logical AND gate and the first or second logic value with delaying for the amount of first delay, a fourth logical AND element which logic-reversed the first logic value and the output of the first logical AND element are inputted to, and when the second input signal is given, instead of logic-reversed the first logic value, logic-reversed the second logic value is inputted to, and outputs an AND of the output of the first logical AND element and logic-reversed the first or second logic value with delaying for the amount of said first delay, a logical OR element which the outputs of the third and fourth logical AND elements are inputted to, and outputs an OR of the third and fourth logical AND elements with delaying for the amount of the second delay, the second pulse, and when the second input signal is given, outputs the first and the second pulses simultaneously a third delay element which the output of the second logical AND element is inputted to, and outputs the output of the second logical AND element with delaying for the amount of the first delay, and a fourth delay element which the output of the third delay element is inputted to, and outputs the output of the third delay element with delaying for the amount of the second delay, as the first pulse.
According to a twentieth aspect of the present invention, a drive circuit according to claim 19, wherein the first inverter element comprises a first inverter circuit which logic-reverses the first input signal and outputs the first input signal, the first delay element comprising a second inverter circuit which logic-reverses the first input signal and outputs the first input signal, and a third inverter circuit which logic-reverses the output of the second inverter circuit and outputs the output of the second inverter circuit, the first logical AND element comprising a first NAND circuit which the outputs of the first inverter element and the first delay element are inputted to, and a fourth inverter circuit which the output of the first NAND circuit is inputted to, the second inverter element comprising a fifth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, the second delay element comprising a sixth inverter circuit which logic-reverses the output of the first inverter element and outputs the output of the first inverter element, and a seventh inverter circuit which logic-reverses the output of the sixth inverter circuit and outputs the output of the sixth inverter circuit, the second logical AND element comprising a second NAND circuit which the outputs of the second inverter element and the second delay element are inputted to, and an eighth inverter circuit which the output of the second NAND circuit is inputted to, the third logical AND element comprising a third NAND circuit which logic-reverses an AND of the output of the second logical AND element and the first or second logic value and outputs the AND, and a ninth inverter circuit which the output of the third NAND circuit is inputted to, the fourth logical AND electrode comprising a fourth NAND circuit which logic-reverses an AND of the output of the first logical AND element and logic-reversed the first or second logic value and outputs the AND, and a tenth inverter circuit which the output of the fourth NAND circuit is inputted to, the logical OR element comprising a first NOR circuit which logic-reverses an OR of the outputs of the third and fourth logical AND element and outputs the OR, and an eleventh inverter circuit which the output of the first NOR circuit is inputted to, the third delay element comprising a fifth NAND circuit which logic-reverses an AND of the output of the second logical AND element and the second logic value and outputs the AND, and a twelfth inverter circuit which the output of the fifth NAND circuit is inputted to, and the fourth delay element comprising a second NOR circuit which logic-reverses an OR of the output of the third delay element and the first logic value and outputs the OR, and a thirteenth inverter circuit which the output of the second NOR circuit is inputted to.
These and other objects, features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.